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2015 IEEE High Performance Extreme Computing Conference (HPEC ‘15) Nineteenth Annual HPEC Conference 15 - 17 September 2015 Westin Hotel, Waltham, MA USA
Extreme Form Factors 1:00-2:40 in Eden Vale A3 Chair: Ken Gregson / MIT Lincoln Laboratory Invited Talk: SpaceVPX Embedded Computing to Meet the Demands of Space Dr. Charles Patrick Collier, Air Force Research Laboratory Invited Talk: TBD Prof. Sertac Karaman, Dept of Aero/Astro - MIT Invited Talk: The IEEE Rebooting Computing Initiative Prof. Tom Conte, Georgia Tech - President IEEE Computer Society Invited Talk: Standards to Facilitate Open Architecture and a COTS Ecosystem Mr. Greg Rocco / MIT Lincoln Laboratory, Dave Tremper / Office of Naval Research Agile Condor: A Scalable High Performance Embedded Computing Architecture Mark Barnell, Courtney Raymond, Air Force Research Lab, Christopher Capraro, Darrek Isereau, SRC The Air Force Research Laboratory Information Directorate Advanced Computing and Communications Division is developing a new computing architecture, designed to provide high performance embedded computing (HPEC) pod solution to meet operational and tactical real-time processing intelligence surveillance and reconnaissance (ISR) missions.  This newly designed system, Agile Condor, is a scalable and HPEC system based on open industry standards that will increase, far beyond the current state-of-the-art, computational capability within the restrictive size, weight and power constraints of unmanned aircraft systems’ external “pod” payloads. The objective with such a system is to explore and develop innovative system solutions to meet future Air Force real-time HPEC; e.g., multi-mission, multi-function ISR processing and exploitation. While the core compute capability can be placed in various environments, our baseline design utilizes a 12-inch diameter flight-certified aeronautics pod that is scalable in length. Agile Condor can be connected to external data sources, or the nose and tail can be made of Radio Frequency (RF) transparent material, enabling the use of various RF sensing technologies within the same aeronautics enclosure. Inside this pod is a lightweight, thermally-efficient industry standard 3U VPX conduction cooled (with unconditioned ambient air) chassis that supports the required board and interface hardware. Agile Condor brings high- performance computing closer to sensors and immediately enables future research and development efforts in neuromorphic computing and autonomous system operations.
Wednesday September 16
2015 IEEE High Performance Extreme Computing Conference (HPEC ‘15) Nineteenth Annual HPEC Conference 15 - 17 September 2015 Westin Hotel, Waltham, MA USA
Extreme Form Factors 1:00-2:40 in Eden Vale A3 Chair: Ken Gregson / MIT Lincoln Laboratory Invited Talk: SpaceVPX Embedded Computing to Meet the Demands of Space Dr. Charles Patrick Collier, Air Force Research Laboratory Invited Talk: TBD Prof. Sertac Karaman, Dept of Aero/Astro - MIT Invited Talk: The IEEE Rebooting Computing Initiative Prof. Tom Conte, Georgia Tech - President IEEE Computer Society Invited Talk: Standards to Facilitate Open Architecture and a COTS Ecosystem Mr. Greg Rocco / MIT Lincoln Laboratory, Dave Tremper / Office of Naval Research Agile Condor: A Scalable High Performance Embedded Computing Architecture Mark Barnell, Courtney Raymond, Air Force Research Lab, Christopher Capraro, Darrek Isereau, SRC The Air Force Research Laboratory Information Directorate Advanced Computing and Communications Division is developing a new computing architecture, designed to provide high performance embedded computing (HPEC) pod solution to meet operational and tactical real-time processing intelligence surveillance and reconnaissance (ISR) missions.  This newly designed system, Agile Condor, is a scalable and HPEC system based on open industry standards that will increase, far beyond the current state-of- the-art, computational capability within the restrictive size, weight and power constraints of unmanned aircraft systems’ external “pod” payloads. The objective with such a system is to explore and develop innovative system solutions to meet future Air Force real-time HPEC; e.g., multi- mission, multi-function ISR processing and exploitation. While the core compute capability can be placed in various environments, our baseline design utilizes a 12-inch diameter flight-certified aeronautics pod that is scalable in length. Agile Condor can be connected to external data sources, or the nose and tail can be made of Radio Frequency (RF) transparent material, enabling the use of various RF sensing technologies within the same aeronautics enclosure. Inside this pod is a lightweight, thermally-efficient industry standard 3U VPX conduction cooled (with unconditioned ambient air) chassis that supports the required board and interface hardware. Agile Condor brings high-performance computing closer to sensors and immediately enables future research and development efforts in neuromorphic computing and autonomous system operations.
Wednesday September 16
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